[1]
Lago, J. et al. 2023. FPGA Digital Architecture for Multilevel Synchronous Optimal PulseWidth ModulationWith Seamless Pulse Pattern Transitions. Eletrônica de Potência. 28, 1 (Mar. 2023), 74–82. DOI:https://doi.org/10.18618/REP.2023.1.0053.