Modeling and Design of a Fast-Dynamic Response Phaselocked Loop Based on Moving Average Filter

Abstract

Phase Locked Loops (PLLs) with in-loop Moving Average Filter (MAF) and a Proportional Integral (PI) controller are effective methods to achieve synchronization in grid-connected converters, since they have simple implementation, low computational burden and excellent filtering capability. However, they are known to be slow. The reasons are the MAF time delay and the PI controller tuning method, which makes the design of a fast control loop challenging. This paper demonstrates that the second-order Padé approximation is enough to achieve an accurate model for the MAF, and presents a controller design technique that results in the minimum settling times achievable for a MAF-PLL with a PI controller. Simulation and experimental results validate the proposed approach.